1. Field of the Invention
This invention relates to a method for making a semiconductor device. This invention particularly relates to an etching process for use in forming a planarized insulating film from an oxide film and an organic spin-on glass film (hereinafter referred to as the "organic SOG film").
2. Description of the Related Art
Planarization of films for layer insulation is important in the formation of multi-layer wiring. In general, organic SOG films are employed to form flat insulating films.
A conventional etching process, which is employed in the formation of a planarized insulating film from an organic SOG film, is carried out in the manner described below. For the etching process of this type, an etching gas, which is constituted of a mixture of trifluoromethane (CHF.sub.3) and oxygen (O.sub.2), is employed. In such cases, the etching rate ratio R of a silicon oxide film to an organic SOG film is approximately 1.0.
FIGS. 4A and 4B are sectional views showing a semiconductor chip as an aid in explaining a conventional etching process.
As illustrated in FIG. 4A, an aluminum wiring 7 having a thickness of 800 nm is formed on a BPSG film 6, which has been overlaid on a silicon substrate 4B. Thereafter, a silicon oxide film 8 is formed to a thickness of 800 nm by the plasma CVD process, and an organic SOG film 9 having a thickness of 300 nm is applied by coating. At this time, part of the organic SOG film 9 corresponding to the position of the aluminum wiring 7 becomes thin, and part of the organic SOG film 9 corresponding to the position free of the aluminum wiring 7 becomes thick. Thereafter, the semiconductor substrate 4B, which has thus been provided with the films, is subjected to an etching process utilizing CHF.sub.3 and O.sub.2. In such cases, from the point of time at which the silicon oxide film 8 becomes exposed, oxygen in the silicon oxide film 8 is fed therefrom into the plasma. Therefore, the etching rate of the organic SOG film 9 increases, and the etching rate ratio of the silicon oxide film 8 to the organic SOG film 9 becomes approximately 0.5.
Therefore, as illustrated in FIG. 4B, in cases where the etching process is carried out until the thickness of part of the silicon oxide film 8 located on the aluminum wiring 7 becomes 200 nm, the organic SOG film 9 is completely removed by etching. Thus a flat shape of the insulating film cannot be obtained.
As described above, with the conventional process for planarizing an insulating film constituted of an organic SOG film, a silicon oxide film located under the organic SOG film becomes exposed during the etching, and oxygen in the silicon oxide film is thereby fed into the plasma. As a result, the etching rate of the organic SOG film becomes higher than that of the silicon oxide film. Therefore, it is difficult to form a flat insulating film having a predetermined thickness. For this reason, the step coverage of an upper wiring becomes bad, and wire breakage occurs. Accordingly, the reliability and yield of semiconductor devices cannot be kept high.